Staff Engineer, IP Dev Layout

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

Responsible for on-time delivery of block-level layouts with acceptable quality.

Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution to meet project scheduling multiple project environment.

Contribute to effective project-management.

Effectively communicating with Global engineering teams to assure the success of layout project.

Qualification/Requirements 8 to 15 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand build constraints and implement high-quality layouts Ability to understand build hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills Should be proactive in exploring and using AI-related tools in day-to-day tasks.

8 to 15 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET )