Staff Engineer, Design Verification Engineering

About the Role

Responsibilities

• Lead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.
• Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals using advanced methodologies.
• Architect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.
• Define and execute test plans; drive functional and code coverage closure in collaboration with design teams.
• Work cross-functionally with emulation, FPGA, and firmware teams to ensure end-to-end system correctness.
• Apply formal verification techniques for IP and subsystem-level validation.
• Lead NoC/interconnect verification and ensure robust data flow across the system.
• Perform system-level use case validation, including performance verification and analysis.
• Develop and validate end-to-end scenarios to ensure real-world functionality.
• Drive innovative verification strategies to meet quality and schedule goals.
• Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

Requirements

• B.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification.
• Strong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience in verification closure using functional and code coverage metrics at block and subsystem levels.
• Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Experience in architecting testbench environments and implementing scalable DV flows and methodologies.
• Hands-on experience in power-aware verification using UPF, including power analysis and optimization.
• Exposure to formal verification, including flow setup, connectivity, and functional checks.
• Familiarity with gate-level simulations (GLS) with timing annotation.
• Strong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling using SystemVerilog.
• Understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures is a plus.
• Proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Excellent communication and collaboration skills with the ability to work across global teams.
• Strong problem-solving ability with a mindset to quickly learn and adopt new technologies.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.