As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description
Role Summary
We are looking for a Staff Design Verification Engineer to lead the verification of complex out‑of‑order (OOO) CPU cores and memory subsystems . In this role you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.
Key Responsibilities
Technical Ownership
Own DV for major OOO core subsystems such as: Front‑end: fetch, branch prediction, instruction decode. Rename / register mapping and dependency tracking. Issue queues / schedulers, execution units, bypass networks. Reorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay. Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores. L1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.
Apply for this job in 1 click
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
Constrained‑random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).
Define and evolve DV methodology for OOO verification: Scenario libraries for speculation, memory ordering, and multi‑core interactions. Reuse patterns across IPs and projects; contribute to common DV infrastructure.
Scenario libraries for speculation, memory ordering, and multi‑core interactions.
Reuse patterns across IPs and projects; contribute to common DV infrastructure.
Coverage, Assertions, and Sign‑off
Define coverage models and sign‑off criteria: Functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.
Functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.
Develop and maintain assertion sets (SVA) for key OOO properties, such as: No deadlock/livelock in ROB / scheduler / LSQ. Correct branch mispredict, exception, and interrupt recovery. Correct load‑store ordering, forwarding, and replay behavior.
No deadlock/livelock in ROB / scheduler / LSQ.
Correct branch mispredict, exception, and interrupt recovery.
Correct load‑store ordering, forwarding, and replay behavior.
Drive coverage closure and sign‑off for owned blocks; review and sign off plans/coverage for peer areas when needed.
Debug & Cross‑Functional Collaboration
Lead debug of complex failures: Subtle OOO bugs (hazards, wrong‑path effects, starvation, corner replay conditions). Memory ordering and coherence violations across cores and caches. TLB/MMU and privilege/protection corner cases.
Memory ordering and coherence violations across cores and caches.
TLB/MMU and privilege/protection corner cases.
Work closely with: Micro‑architecture and RTL teams to refine designs for correctness and verifiability. Performance/modeling teams to align micro‑arch behavior with models and performance targets. Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.
Micro‑architecture and RTL teams to refine designs for correctness and verifiability.
Performance/modeling teams to align micro‑arch behavior with models and performance targets.
Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.
Mentoring & Influence
Mentor junior and mid‑level DV engineers in: OOO micro‑architecture concepts and debug. Testbench design, stimulus generation, coverage, and methodology.
OOO micro‑architecture concepts and debug.
Testbench design, stimulus generation, coverage, and methodology.
Provide technical leadership across projects: Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective. Champion best practices in DV and help set technical direction for core verification.
Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective.
Champion best practices in DV and help set technical direction for core verification.
Required Qualifications
Education : BS/MS/PhD in EE, CE, CS, or related field.
Experience : Typically 8+ years of hands‑on ASIC/SoC/IP design verification experience. Significant experience verifying out‑of‑order or superscalar CPU cores or similarly complex execution pipelines.
Typically 8+ years of hands‑on ASIC/SoC/IP design verification experience.
Significant experience verifying out‑of‑order or superscalar CPU cores or similarly complex execution pipelines.
Technical Skills : Strong proficiency in SystemVerilog and UVM (or equivalent class‑based methodology). Deep understanding of CPU micro‑architecture, including several of: Front‑end (fetch, branch prediction, decode). Rename, physical register files, dependency tracking. Schedulers/issue queues, execution units, bypassing. ROB, commit logic, exception/interrupt/flush paths. LSU, store buffer, speculative loads/stores, atomics and fences. L1 caches, TLBs, MMU, and coherence interfaces. Solid experience with: Constrained‑random, coverage‑driven verification. Writing and debugging SVA assertions . Major simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
Strong proficiency in SystemVerilog and UVM (or equivalent class‑based methodology).
Deep understanding of CPU micro‑architecture, including several of: Front‑end (fetch, branch prediction, decode). Rename, physical register files, dependency tracking. Schedulers/issue queues, execution units, bypassing. ROB, commit logic, exception/interrupt/flush paths. LSU, store buffer, speculative loads/stores, atomics and fences. L1 caches, TLBs, MMU, and coherence interfaces.
LSU, store buffer, speculative loads/stores, atomics and fences.
L1 caches, TLBs, MMU, and coherence interfaces.
Solid experience with: Constrained‑random, coverage‑driven verification. Writing and debugging SVA assertions . Major simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
Constrained‑random, coverage‑driven verification.
Writing and debugging SVA assertions .
Major simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
Soft Skills : Strong problem‑solving and debug skills for complex concurrency/ordering issues. Proven ability to drive technical topics across teams and to completion. Clear communication, both written and verbal; able to present designs, plans, and status to technical and non‑technical stakeholders.
Strong problem‑solving and debug skills for complex concurrency/ordering issues.
Proven ability to drive technical topics across teams and to completion.
Clear communication, both written and verbal; able to present designs, plans, and status to technical and non‑technical stakeholders.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
About SiFive
Semiconductors588 employeesFounded 2015
SiFive is a private RISC-V processor-IP company licensing proprietary cores and technology to chip and system developers.
