Staff Design Verification Engineer – CPU Core Verification (Vector)

About the Role

Responsibilities

• Own verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level verification through core-level integration and signoff.
• Drive verification strategy, test planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural interactions.
• Define effective verification approaches for challenging behaviors such as branch prediction, instruction fetch, issue and dispatch behavior, pipeline interactions, hazard handling, load/store ordering, memory consistency, exception and recovery behavior, hardware prefetch correctness, and vector execution correctness.
• Drive verification of RVV and vector-unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration-dependent execution, hazard handling, exception behavior, and scalar-vector interactions.
• Verify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register-file behavior, vector memory sequencing, and interaction with scalar pipeline and cache / memory hierarchy behavior.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
• Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.
• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Contribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs.
• Mentor other engineers through technical reviews, debugging guidance, and stronger verification practices.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
• Experience in one or more CPU core areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, Hardware Prefetch, or Vector Unit verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.
• Familiarity with Python, C/C++, or similar scripting/programming languages used for DV infrastructure and automation.

Preferred Qualifications

• Direct experience with high-performance out-of-order CPU core verification.
• Direct experience with RISC-V Vector Extension (RVV), SIMD, or vector-processor verification.
• Experience verifying vector behaviors such as vector arithmetic, masking, reductions, permutations, vector-scalar operations, and vector load/store functionality.
• Experience verifying vector memory behavior, including alignment, page-boundary conditions, exception handling, hazard detection, cache/memory interactions, and coherency-sensitive scenarios.
• Experience working with vector configuration and execution modes such as SEW, LMUL, VL, VSTART, and related legality / corner-case behavior.
• Experience verifying complex CPU microarchitectural behaviors involving concurrency, replay, flush, redirects, dependency handling, or weak memory ordering.
• Experience developing high-value assertions, checkers, and scoreboards for control-heavy or ordering-sensitive CPU behavior.
• Experience using formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems.
• Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
• Experience influencing verification methodology beyond immediate ownership scope through reusable infrastructure, automation, or technical leadership.
• You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.
• BS/MS Degree in EE, CE or CS
• 5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification
• Deep understand of computer architecture is desired
• Experienced developer using Object Oriented Programing principles
• In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
• Additional Information:
• This position requires a successful background and reference checks and satisfactory proof of your right to work in
• Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
• SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
• As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.