indeed
Staff Design Verification Engineer
SiFive
IND
Full-time
Onsite
Discovered 1 weeks ago
SystemVerilogUVMOut-of-order CPU microarchitectureASIC/SoC/IP design verificationCoverage-driven verificationCoverage closure
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SystemVerilogUVMOut-of-order CPU microarchitecture
Role Overview
Own verification strategy and execution for complex out-of-order processors and cache or memory subsystems.
Drive verification of speculative execution, memory ordering, and coherence features from architecture through tape-out.
Key Skills for This Role
SystemVerilogUVMOut-of-order CPU microarchitectureASIC/SoC/IP design verificationCoverage-driven verificationCoverage closure
Full Job Posting
About SiFive
SiFive develops RISC-V compute platforms for demanding applications across artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.
The company emphasizes collaborative teams, processor innovation, and inclusive employment practices.
Role Overview
Own verification strategy and execution for complex out-of-order processors and cache or memory subsystems.
Drive verification of speculative execution, memory ordering, and coherence features from architecture through tape-out.
Verification Ownership
- Verify out-of-order front-end, back-end, retirement, recovery, and memory subsystems.
- Define test plans from ISA and microarchitecture specifications, including speculative execution, memory consistency, and coherence behavior.
- Drive functional, code, assertion, and scenario coverage closure to sign-off criteria.
Testbench and Modeling
- Architect constrained-random, coverage-driven UVM testbenches for processor pipelines, cache and memory hierarchies, TLBs, IOMMUs, and coherence protocols.
- Develop generators, monitors, scoreboards, and protocol checkers for out-of-order stress scenarios.
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