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Staff Design Verification
SiFive
IND
Full-time
Onsite
Discovered 1 weeks ago
ASIC/SoC/IP design verificationOut-of-order CPU verificationCPU microarchitectureSystemVerilogUVMConstrained-random verification
Free
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ASIC/SoC/IP design verificationOut-of-order CPU verificationCPU microarchitecture
Role Overview
Staff Design Verification Engineer role leading verification of complex out-of-order CPU cores and memory subsystems.
Own verification strategy, methodology, execution, coverage, and sign-off for major core blocks.
Act as a technical leader and mentor within the design verification team.
Key Skills for This Role
ASIC/SoC/IP design verificationOut-of-order CPU verificationCPU microarchitectureSystemVerilogUVMConstrained-random verification
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About SiFive
SiFive develops RISC-V compute platforms for applications including artificial intelligence, automotive, data centers, mobile, and consumer products.
Role Summary
Staff Design Verification Engineer role leading verification of complex out-of-order CPU cores and memory subsystems.
Own verification strategy, methodology, execution, coverage, and sign-off for major core blocks.
Act as a technical leader and mentor within the design verification team.
Technical Ownership
- Own verification for front-end, rename, scheduling, execution, retirement, load-store, cache, TLB, MMU, and coherence subsystems.
- Translate ISA and microarchitecture specifications into detailed verification plans and test strategies.
Testbench and Methodology
- Architect reusable SystemVerilog/UVM environments with agents, monitors, scoreboards, and reference models.
- Develop constrained-random and targeted stimulus for speculation, hazards, reorder stress, and memory interactions.
- Define scenario libraries and reusable design verification infrastructure across IPs and projects.
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