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Staff Analog IC Engineer
Semtech
Hyderabad, IND
Full-time
Senior · 6+ years experience
Onsite
Discovered 2 weeks ago
CadenceVerilog-AMSSystemVerilogLVSDRCPEX
Free
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CadenceVerilog-AMSSystemVerilog
Key Skills for This Role
CadenceVerilog-AMSSystemVerilogLVSDRCPEX
Full Job Posting
Responsibilities
- Support the design and development of high-accuracy analog and mixed-signal ICs, delivering robust, high-quality designs that meet defined specifications and timelines (55%).
- Take ownership of critical chip subsystems and act as domain expert (20%).
- Collaborate closely with Marketing, Product Definition, Test, Verification, Reliability, and Product Engineering teams to ensure successful product development (10%).
- Drive innovation in circuit design and architecture, introducing new ideas and solutions to improve performance and efficiency (5%).
- Communicate complex technical concepts clearly through reports and presentations to senior stakeholders (10%).
Minimum Qualifications
- Bachelor’s degree in electrical, electronics, or related Engineering field with 6+ years’ experience in analog IC design within the semiconductor industry.
- Deep understanding of CMOS/BiCMOS analog circuit design practices.
- Proven experience as a technical lead on chip development projects.
- Strong mixed-signal design experience.
- Expert proficiency with Cadence design environment, simulation, and verification tools.
- Expert proficiency with device modelling (Verilog-AMS, SystemVerilog) and mixed-signal simulation.
- Understanding of design for manufacturability (DFM), reliability, and yield optimization.
- Solid understanding of mixed-signal design, including parasitic, matching, ESD, latch up, crosstalk, and IR drop.
- Experience in chip top level verification and production experience is a plus
- Documentation of design results, characterization results and DFMEA
- Experience in translating MEMS models into equivalent circuits
- Demonstrated innovation and creative problem-solving capabilities.
- Analog block and full chip level schematic design, process corner analysis, and post-layout simulation
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