indeed
Sr Staff Mixed-Signal Verification Engineer
Synopsys
IND
Onsite
Discovered 1 weeks ago
Mixed-signal verificationSystemVerilogUVMCoverage-driven verificationConstrained-random verificationVerilog-A and Verilog-AMS
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Mixed-signal verificationSystemVerilogUVM
Role Overview
The role focuses on mixed-signal verification for complex semiconductor IP at Synopsys.
The engineer owns verification methodology, test plans, coverage, debug strategies, and sign-off through tapeout readiness.
The position combines analog circuit understanding with digital verification, behavioral modeling, and automation.
Key Skills for This Role
Mixed-signal verificationSystemVerilogUVMCoverage-driven verificationConstrained-random verificationVerilog-A and Verilog-AMS
Full Job Posting
Role Overview
The role focuses on mixed-signal verification for complex semiconductor IP at Synopsys.
The engineer owns verification methodology, test plans, coverage, debug strategies, and sign-off through tapeout readiness.
The position combines analog circuit understanding with digital verification, behavioral modeling, and automation.
What You'll Be Doing
- Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems.
- Build UVM/SystemVerilog environments integrating Verilog-A, Verilog-AMS, and mixed-signal simulators.
- Debug analog-digital interface issues, convergence problems, and cross-domain failures using waveforms and AMS tools.
- Develop assertions, monitors, scoreboards, and automated verification infrastructure.
- Improve simulation efficiency, optimize regression flows, and reduce debug turnaround time.
- Collaborate with analog designers, digital verification engineers, modeling teams, and architecture groups.
- Mentor verification engineers and drive AMS methodology and best practices across the team.
What You'll Need
- At least 8 years of hands-on AMS verification experience with a proven record of owning mixed-signal verification sign-off.
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