Sr. Staff Engineer PD

Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features Execute all phases of physical design: synthesis, floorplanning, placement, clock tree synthesis, place-and-route, timing closure, power/noise analysis, and signoff verification.

Implement design strategies to achieve performance, area, and power targets for customer-specific ICs under lead guidance.

Apply re-use methodologies, leveraging standard IP blocks, libraries, and flows to accelerate project execution.

Resolve timing, congestion, and power issues in high-speed, high-density designs using EDA tools and scripting.

Collaborate with RTL design, verification, DFT, and package teams to integrate requirements and ensure design convergence.

Perform physical verification (DRC, LVS) and support debug for clean tape-out deliverables.

Automate flows with TCL, Python, or Perl scripts to improve productivity and repeatability.

Analyze design metrics and contribute to process improvements through data-driven insights.