Principal STA Engineer

We are seeking a highly skilled Principal STA Engineer to serve as the technical authority for signoff timing convergence within our Physical Design organization. This role requires deep expertise in STA, strong hands‑on execution, and the ability to define and drive shift‑left signoff strategies. You will collaborate closely across teams on constraints, optimization, and timing analysis to ensure predictable, high‑quality SoC closure.

Own SoC‑level signoff STA, including timing ECO delivery and GLS enablement.

Drive robust co‑optimization strategies to achieve benchmark PPAS targets.

Develop and maintain PPAS/status dashboards using scripting automation.

Collaborate with RTL Design, Verification, Physical Design, and DFT teams to ensure design convergence and consistent signoff.

Rationalize timing margins with minimal supervision.

Analyze design metrics and collateral to propose data‑driven process improvements.

Apply reuse methodologies for IP, libraries, and flows to accelerate execution.

Automate and enhance STA flows using TCL, Python, or Perl to improve productivity and repeatability.