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Sr. Staff Engineer, Full-chip Physical Verification and Foundry Sign Off
Ayar Labs
Bengaluru, IND
Full-time
Senior · 8+ years experience
Onsite
Discovered 3 weeks ago
Siemens Calibre nmDRCCadence PegasusSynopsys ICVLEFDEFGDSII
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Siemens Calibre nmDRCCadence PegasusSynopsys ICV
Key Skills for This Role
Siemens Calibre nmDRCCadence PegasusSynopsys ICVLEFDEFGDSII
Full Job Posting
- Own full-chip physical-verification methodology, execution, closure, and final tapeout certification.
- Drive DRC, LVS, ERC, PERC, antenna, density, DFM, metal-fill, XOR, and connectivity closure.
- Develop and maintain hierarchical and incremental PV flows for large mixed-signal SoCs.
- Resolve complex LVS issues involving hierarchy, black boxes, analog/custom blocks, multiple power domains, global nets, CDL/SPICE netlists, and parameterized devices.
- Own top-level verification of pad rings, bumps, RDL, seal rings, ESD structures, power connectivity, analog interfaces, and custom layout.
- Qualify foundry rule decks, runsets, tool versions, PDK updates, and signoff configurations.
- Establish processes for violation classification, ownership, review, waiver approval, and foundry disposition.
- Coordinate metal-fill generation and post-fill timing, extraction, EMIR, DRC, LVS, and density rechecks.
- Maintain auditable signoff checklists, dashboards, release criteria, database checksums, and tapeout-quality gates.
- Own final GDS/OASIS stream-out verification and foundry handoff.
- Work directly with physical design, analog layout, DFT, package, reliability, foundry, EDA, and external ASIC service teams.
- Automate repetitive PV analysis, reporting, triage, and regression activities.
- Mentor engineers and establish consistent PV practices across blocks and projects.
- BS or MS in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of ASIC physical verification or physical design experience.
- Demonstrated full-chip PV ownership on at least three successful tapeouts.
- Hands-on experience with N3/N3P or comparable leading-edge process nodes.
- Mastery of Siemens Calibre nmDRC/nmLVS and experience with Cadence Pegasus or Synopsys ICV.
- Deep knowledge of DRC, LVS, ERC, PERC, antenna, density, metal-fill, DFM, and XOR methodologies.
- Experience debugging hierarchical, mixed-signal, multi-voltage, and top-level LVS problems.
- Strong knowledge of LEF, DEF, GDSII, OASIS, CDL, SPICE, Verilog netlists, and layout connectivity.
- Proficiency in Tcl, Python, Perl, shell, or SVRF-based automation.
- Experience working directly with foundry rule decks, technical support, and waiver processes.
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