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Sr. Staff Engineer, Electrical Link Architecture
Ayar Labs
San Jose, USA
Full-time
Senior Level
Onsite
USD 190000-223000 yearly
Discovered 1 weeks ago
Free
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- Build and maintain compact models of the analog front end and the DSP chain at the fidelity needed for accurate BER and link-margin prediction.
- Co-design Verilog-A models of the electrical/optical interface — modulators, photodetectors, and the blocks where circuits and photonics meet — with analog / mixed-signal (AMS) designers.
- Anchor models to silicon by working with validation engineers to reconcile simulation against measurement.
- Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
- Collaborate across AMS, photonics, and validation to keep the modeling stack coherent with the product roadmap.
- Run end-to-end link simulations to evaluate device and architecture choices, informing current product design and future roadmap exploration.
- MS in Electrical Engineering, Physics, or a related field.
- 5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
- Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
- Proficiency in Verilog-A and mixed-signal simulation methodologies.
- Experience with statistical circuit analysis methods (corners, Monte Carlo).
- Strong Python skills for scientific computing and data analysis.
- Prior industry experience architecting and deploying SerDes into a shipping product.
- Ph.D.
- Hands-on experience with silicon bring-up, validation, or link characterization.
- Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
- Familiarity with Cadence Virtuoso / ADE / Spectre.
- Familiarity with optical transceiver principles, modulation formats, and industry standards.
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