Sr Staff Engineer DFT

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com .

Architectural Leadership: Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet -based designs.

Test Strategy Optimization: Develop advanced strategies for defect-oriented testing (Cell-aware, Slack-aware) and optimize pattern volumes to balance aggressive coverage targets with tester memory constraints.

Cross-Functional Integration: Lead the integration of DFT requirements into RTL, Synthesis, and Physical Design (STA/PD) flows. Drive "Design for Manufacturability" (DFM) initiatives to improve yield.

Silicon Bring-up & Debug: Spearhead post-silicon validation and silicon bring-up. Own the root-cause analysis of complex test failures and provide expert-level debugging of ATE/System-level failures.

Methodology & Automation: Architect and maintain scalable, high-performance DFT flows using TCL, Python, or Perl. Evaluate and benchmark emerging EDA tool features to stay ahead of technology nodes (5nm/3nm and beyond).

Mentorship & Influence: Provide technical mentorship to junior and senior engineers. Act as a consultant for verification and backend teams to resolve "bottleneck" timing or routing issues caused by DFT structures.

Technical Documentation: Author comprehensive DFT specifications and strategy documents that serve as the "Gold Standard" for current and future project iterations.