AI/ML Compiler & Runtime Software Engineer

Role overview

Core responsibilities

• Architect and develop AI/ML compiler and runtime software for RISC-V, NPU, and SoC platforms.
• Develop IREE compiler flows covering MLIR lowering, code generation, runtime integration, and edge deployment.
• Create custom MLIR dialects, compiler passes, lowering pipelines, and accelerator code generation flows.
• Optimize neural network workloads using fusion, tiling, memory planning, quantization, layout transformation, and accelerator-aware scheduling.
• Bring up workloads across simulators, FPGA platforms, emulation environments, and silicon with cross-functional teams.
• Analyze performance bottlenecks and optimize graph-, operator-, and kernel-level execution.
• Define AI SDK architecture, runtime interfaces, deployment flows, and accelerator integration.
• Build tests, validation flows, benchmarks, and CI pipelines for correctness and performance.
• Provide technical leadership, mentoring, debugging, performance tuning, and deployment support.

Required qualifications

• Have 3-12 years of hands-on software engineering experience in compiler, runtime, embedded software, or AI/ML systems.
• Have strong experience with IREE, LLVM, and MLIR compiler infrastructure.
• Have experience with MLIR dialects, compiler passes, lowering pipelines, pattern rewrites, code generation, or custom hardware backends.
• Understand IREE code generation, dispatch formation, executable generation, HAL/runtime concepts, and target-specific lowering.
• Have experience with AI model formats and frameworks such as PyTorch, ONNX, and TensorFlow Lite.
• Understand neural network execution and optimization, including quantization, fusion, layouts, memory planning, tiling, vectorization, and kernel selection.
• Have experience with AI accelerators, NPUs, DSPs, vector processors, matrix engines, or custom SoC IP.
• Have strong C/C++ skills, Python scripting ability, Linux development experience, and strong debugging skills.
• Be able to collaborate with hardware and architecture teams and technically lead complex software modules.

Preferred experience

• Experience with RISC-V, ARM, x86, DSP, GPU, or custom accelerator software stacks.
• Familiarity with RISC-V Vector, matrix acceleration, custom instructions, or accelerator-specific code generation.
• Experience with edge AI deployment on devices, development boards, FPGA platforms, emulators, simulators, or early silicon.
• Familiarity with llama.cpp, GGML/GGUF, ONNX Runtime, TensorFlow Lite, TVM, XNNPACK, or similar edge inference stacks.
• Experience benchmarking AI workloads for vision, audio, transformers, GenAI, robotics, automotive, industrial, or embedded use cases.
• Understanding of hardware-software co-design, memory hierarchy, DMA, scratchpad memory, cache behavior, and accelerator data movement.
• Experience with runtime systems, kernel libraries, microkernels, custom dispatch flows, or accelerator runtime APIs.
• Familiarity with Jenkins, Git, CMake, Bazel, Jira, or similar engineering infrastructure.

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