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Sr. Design Verification Engineer

Credo
San Jose, USA
Full-time
Senior Level
Onsite
USD 130000-160000 yearly
Discovered 1 weeks ago
Free

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Job Description

  • Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
  • People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
  • Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Job requirements

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • 7+ years of experience in RTL and functional verification using SV/UVM.
  • PCIe verification experience.
  • Experience with gate‑level simulation and firmware‑based simulation.
  • Proficiency in RTL design and computer architecture concepts.
  • Strong debugging, problem‑solving, and analytical skills.
  • Effective collaborator who thrives in cross‑functional teams.
  • Background in high‑speed connectivity solutions (PCIe/CXL, SerDes, optical DSP).
  • Experience working across HW/SW boundaries and with application engineering/firmware teams.
  • PHY verification experience.

Job responsibilities

  • Understand design intent and develop comprehensive verification & test plans.
  • Develop reusable, scalable SV‑UVM testbenches and write test sequences.
  • Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller).
  • Write assertions, checkers, and coverage, analyze functional & code coverage gaps, and drive closure.
  • Build firmware‑based simulations in C; mirror/approximate real FW behavior to validate HW/SW interactions.
  • Reproduce silicon failures in simulation and perform deep debug to root cause.
  • Automate flows with Python/Perl/Shell scripting.
  • Collaborate with AEs/FW on debug, feature implementation, and spec contributions driven by DV findings.

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