SoC Memory Subsystem Architect

Qualifications

• 10+ years of experience in Silicon architecture or IP design mainly focusing on memory subsystem.
• Strong understanding of distributed AI training system's requirement on SoC memory subsystem.
• Demonstrated experience in HW digital design and understanding of CPU/HW Accelerators and/or Peripheral design.
• Familiarity with SW and Operating system practices and requirements on memory system.
• Experience in System Performance analysis and debug in pre and/or Post-Silicon environments.
• Solid background of System interconnect, System MMUs, Caches and Memory Technologies (e.g. HBM, GDDR, DDR and LPDDR4/5).
• Experience with data analysis using Excel, Perl, Python etc.
• Master or PhD in Electrical or Computer Engineering.
• Excellent communication skills in both English and Chinese.
• Culture Fit:
• Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
• Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
• Hungry to learn: We are eager to see you learn new skills and grow.
• Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.
• #LI-DNI