Senior Technical Lead – Post-Silicon Validation & RTOS SDK

Our Key Differentiators

Key Responsibilities

• Team Leadership Build and lead a 10+ member cross-functional embedded software team . Define execution plans, schedules, and quality metrics across SDK and AVV. Mentor team members; provide guidance on technical challenges and project delivery.
• Build and lead a 10+ member cross-functional embedded software team .
• Define execution plans, schedules, and quality metrics across SDK and AVV.
• Mentor team members; provide guidance on technical challenges and project delivery.
• RTOS SDK Development Own the architecture and delivery of the RTOS SDK (FreeRTOS, other) , including BSPs, HALs, low-level drivers, and middleware. Ensure modular, scalable SDK structure supporting AUTOSAR and non-AUTOSAR stacks. Deliver example applications and customer reference packages. Drive code reuse across internal validation and customer deliverables.
• Own the architecture and delivery of the RTOS SDK (FreeRTOS, other) , including BSPs, HALs, low-level drivers, and middleware.
• Ensure modular, scalable SDK structure supporting AUTOSAR and non-AUTOSAR stacks.
• Deliver example applications and customer reference packages.
• Drive code reuse across internal validation and customer deliverables.
• Post-Silicon AVV Define and execute software-centric AVV strategy for post-silicon validation. Validate key subsystems: ADCs, PWMs, Ethernet, timers, watchdogs, CAN, LIN, FlexRay , etc. Lead first-silicon bring-up , in-depth debugging, and regression testing. Implement AVV use cases covering functional, real-time, and safety behaviours. Ensure ASIL-D level functional safety validation , using SIL, HIL, and fault injection. Build automation infrastructure supporting lab validation and CI pipelines.
• Define and execute software-centric AVV strategy for post-silicon validation.
• Validate key subsystems: ADCs, PWMs, Ethernet, timers, watchdogs, CAN, LIN, FlexRay , etc.
• Lead first-silicon bring-up , in-depth debugging, and regression testing.
• Implement AVV use cases covering functional, real-time, and safety behaviours.
• Ensure ASIL-D level functional safety validation , using SIL, HIL, and fault injection.
• Build automation infrastructure supporting lab validation and CI pipelines.
• Cross-Functional Collaboration Work closely with system architects, hardware, and safety teams. Provide feedback to hardware design and influence next-gen RISC-V CPU and SoC features. Interact with internal and external stakeholders to align roadmaps and execution.
• Work closely with system architects, hardware, and safety teams.
• Provide feedback to hardware design and influence next-gen RISC-V CPU and SoC features.
• Interact with internal and external stakeholders to align roadmaps and execution.
• Customer & Ecosystem Engagement Collaborate with OEM/Tier-1 customers on integration, onboarding, and SDK adoption. Contribute to the RISC-V open-source ecosystem , including toolchain, RTOS, and libraries
• Collaborate with OEM/Tier-1 customers on integration, onboarding, and SDK adoption.
• Contribute to the RISC-V open-source ecosystem , including toolchain, RTOS, and libraries

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