Senior / Staff / Sr. Staff Engineer - Design Verification

Own DV for major OOO core subsystems such as: Front‑end: fetch, branch prediction, instruction decode. Rename / register mapping and dependency tracking. Issue queues / schedulers, execution units, bypass networks. Reorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay. Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores. L1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.

Front‑end: fetch, branch prediction, instruction decode.

Rename / register mapping and dependency tracking.

Issue queues / schedulers, execution units, bypass networks.

Reorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay.

Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores.

L1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.

Translate ISA + micro‑architecture specifications into detailed verification plans and test strategies.

Architect and implement System Verilog/UVM testbenches for OOO cores and subsystems: Reusable UVM environments, agents, monitors, scoreboards, reference models. Constrained‑random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).

Reusable UVM environments, agents, monitors, scoreboards, reference models.

Constrained‑random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).

Define and evolve DV methodology for OOO verification: Scenario libraries for speculation, memory ordering, and multi‑core interactions. Reuse patterns across IPs and projects; contribute to common DV infrastructure.

Scenario libraries for speculation, memory ordering, and multi‑core interactions.

Reuse patterns across IPs and projects; contribute to common DV infrastructure.

Define coverage models and sign‑off criteria: Functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.

Functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.

Develop and maintain assertion sets (SVA) for key OOO properties, such as: No deadlock/livelock in ROB / scheduler / LSQ. Correct branch mispredict, exception, and interrupt recovery. Correct load‑store ordering, forwarding, and replay behavior.

No deadlock/livelock in ROB / scheduler / LSQ.

Correct branch mispredict, exception, and interrupt recovery.

Correct load‑store ordering, forwarding, and replay behavior.

Drive coverage closure and sign‑off for owned blocks; review and sign off plans/coverage for peer areas when needed.

Lead debug of complex failures: Subtle OOO bugs (hazards, wrong‑path effects, starvation, corner replay conditions). Memory ordering and coherence violations across cores and caches. TLB/MMU and privilege/protection corner cases.

Subtle OOO bugs (hazards, wrong‑path effects, starvation, corner replay conditions).

Memory ordering and coherence violations across cores and caches.

TLB/MMU and privilege/protection corner cases.

Work closely with: Micro‑architecture and RTL teams to refine designs for correctness and verifiability. Performance/modeling teams to align micro‑arch behavior with models and performance targets. Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.

Micro‑architecture and RTL teams to refine designs for correctness and verifiability.

Performance/modeling teams to align micro‑arch behavior with models and performance targets.

Post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.

Mentor junior and mid‑level DV engineers in: OOO micro‑architecture concepts and debug. Testbench design, stimulus generation, coverage, and methodology.

OOO micro‑architecture concepts and debug.

Testbench design, stimulus generation, coverage, and methodology.

Provide technical leadership across projects: Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective. Champion best practices in DV and help set technical direction for core verification.

Lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective.

Champion best practices in DV and help set technical direction for core verification.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.