Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

Your verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally

The testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization

Your coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio

The protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs

Your technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team

The mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish

Your collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience

Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up

Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements

Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff

Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim

Experience with verification IP development, assertion-based verification, or formal methods is a strong plus

Knowledge of modern SoC architectures and high-speed communication interfaces is a plus

You can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them

When a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup

You know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align

You can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact

You are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan

You see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters

You will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.