Senior Power Integrity Engineer - LPU Packaging

NVIDIA is now looking for a Senior Power Integrity Engineer to join our LPU Packaging team!

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years.

It’s a unique legacy of innovation that’s fueled by great technology—and amazing people!

Today, we’re tapping into the unlimited potential of AI to define the next era of computing.

An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

Doing what’s never been done before takes vision, innovation, and the world’s best talent.

What you’ll be doing:

• Define best‑in‑class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle
• Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high‑speed SerDes
• Architect package‑level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
• Drive system‑level PI design, including board‑level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams
• Perform PI extraction and simulation for advanced packages and develop integrated chip–package–board co‑simulation flows using industry-standard tools
• Generate and deploy reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partners
• Define and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications
• Debug complex system‑level issues including rail noise, jitter‑induced errors, resets, and margin loss during hardware testing and validation

What we need to see:

• MS or PhD in Electrical Engineering or a related field, or equivalent experience
• 12+ years of relevant work experience in Power Integrity
• A strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs
• Proven ownership of the chip-package-board PDN design and sign-off process
• Hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages
• Direct experience in the co-design of bump/ball maps, power/ground planes, and decoupling capacitor networks