Senior Memory Subsystem Architect

Developing architecture and micro-architecture to improve the state-of-the-art in memory system optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.

Performance modeling and simulation of features to improve memory system efficiency.

Implementing and maintaining high-level performance and functional models.

Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.

Debugging performance and functional issues with high-level models, RTL simulation, and silicon.

Working with various cross functional teams like ASIC design and verification, software, product development team, marketing in developing the comprehensive solution.

Master degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field (or the equivalent experience).

4+ years of meaningful work experience in SoC Architecture and development specifically in one or more domains of MMU and address translation, memory caching, interconnects, and DRAM controllers.

Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team.

Significant understanding of Performance (Bandwidth and Latency), Quality of Service and its impact on the overall system performance

Practical experience in developing and using Performance model for early Architecture analysis

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