Senior Memory Mask Design Engineer

We are looking for a Senior Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.

NVIDIA has continuously reinvented itself.

Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.

Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world.

This is our life’s work , to amplify human creativity and intelligence.

As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

Come join our diverse team and see how you can make a lasting impact on the world!

What you'll be doing:

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.
• Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.
• Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.
• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.
• Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.
• Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.
• Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.
• Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.
• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.