Senior IP DV Engineer - NOC IP

You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.

Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.

Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.

Work on advanced verification methodologies like SV/UVM.

Perform functional coverage driven verification closure.

Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

B.Tech./ M.Tech., or equivalent experience.

5+ years of relevant experience.

Experience in verification of complex IPs/units and sub-systems.

Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.

Expertise in Verilog.

Knowledge in SystemVerilog or similar HVL / UVM or VMM.

Experience in memory subsystem or network interconnect IP verification.

Good debugging and analytical skills with sound scripting knowledge.

Good communication and excellent team player.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.