Senior Formal Verification Engineer - LPU

Main task: Verify AI-related sophisticated ASIC designs & features with formal verification methods.

Multi-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions.

Formal verification execution: Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities.

Articulate formal verification coverage to partners

Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency

Mentorship: Train and coach junior engineers on formal techniques and standard processes; Help on methodology/FAQ documentation.

Support silicon bring-up and debug using formal methods where it applies.

BS/MS/PhD or equivalent experience in CS/CE/EE.

12+ years in ASIC verification with 8+ years focused on formal verification methods

Mastery of SystemVerilog Assertions (SVA) and formal property verification

Proficient on at least one popular formal verification tool in the industry(JapserGold, VC Formal, etc.)

Good scripting skills for flow automation(tcl, python, etc.)

Good written and oral communication skills

Keen attention to details

Shown success in full-cycle formal sign-off for complex designs