Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 3+ years of experience in SOC or ASIC design and architecture
• Prior direct experience (> 7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

• Experience with BookSim Simulator
• Experience with Platform Architect

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In applying to Samsung and progressing through the recruitment process, you must not disclose any trade secrets of a current or previous employer.

This position will be performed in an office setting.

The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.

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