Base Career helps you apply smarter for this job.
Key skills for this role
Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an Physical Synthesis Engineer, you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.
At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!
We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.
Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
Perform formal or equivalence check on the netlist at block or top level.
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
Santa Clara, USA
Grow with us Ericsson Inc. does not sponsor U.S work authorizations for this job position including U.S. immigration filings for initial and/or change of employer paperwork for H-1's, H-1B1's, E-3's, O-1's, and TN's. Eri
Reading, GBR
Grow with us We are seeking a curious, creative, business-minded lawyer to join the Group Function Legal Affairs team at Ericsson, supporting the Ericsson Enterprise Wireless Solutions (EEWS) business. You will play a ke
Santa Clara, USA
Grow with us About this opportunity: Ericsson Inc. does not sponsor U.S work authorizations for this job position including U.S. immigration filings for initial and/or change of employer paperwork for H-1’s, H-1B1’s, E-3
Plano, USA
Grow with us Financial Analyst Intern Location: Plano, Tx Duration: 12 weeks Start date: May 25th, 2027 Please upload your unofficial transcript when applying. Ericsson Inc. does not sponsor U.S work authorizations for t
Morristown, USA
Join our Team Ericsson Inc. does not sponsor U.S work authorizations for this job position including U.S. immigration filings for initial and/or change of employer paperwork for H-1's, H-1B1's, E-3's, O-1's, and TN's. Er
Austin, USA
Grow with us About this opportunity: EDA Infrastructure Architect Compute and AI, Austin, Texas On-site Hybrid position. This is not a remote work opportunity. Team: Silicon Infrastructure (10-person team) About the Role
, USA
, USA
Santa Clara, USA
Reading, GBR
Santa Clara, USA
Plano, USA
Morristown, USA
Austin, USA
Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.
Manage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs.
Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.
Run block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners.
Support MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams.
Review and validate SDC constraints developed during synthesis against post-layout STA results.
Contribute to clock domain crossing (CDC) checks and timing exception audits during signoff.
Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
Understanding of PTPX-based power analysis flows
DFT synthesis experience (scan, BIST, boundary scan)
Familiarity with congestion-aware and timing-driven P&R closure
Design Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.
B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field.
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts.
Excellent scripting and automation skills; comfort with large, multi-million gate designs.
Strong communication skills — able to clearly present QoR status, risks, and trade-offs to cross-functional teams.
Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: India (IN) || Bangalore
Req ID: 783577
Global provider of communications technology, software, and services.
Visit company websiteJobs and hiring trendsFull-time
Senior · 8+ years experience
Onsite
Apply faster on company sites with our extension.