Senior Electrical Engineer - ASIC/FPGA (Onsite)

Location:

• Position Role Type:
• U.S. Citizen, U.S. Person, or Immigration Status Requirements:
• Security Clearance Type:
• Security Clearance Status:
• Joining Collins Aerospace isn’t just about finding a job; it’s about embarking on a journey to redefine the future of aerospace technology.
• Collins Aerospace, an RTX company, is a leader in technologically advanced and intelligent solutions for the global aerospace and defense industry. Collins Aerospace has the capabilities, comprehensive portfolio, and expertise to solve customers’ toughest challenges and to meet the demands of a rapidly evolving global market.
• We are looking for a Senior FPGA Engineer to be involved in the design, implementation, verification, and integration of a wide variety of high-performance digital ASICs, FPGAs, and circuit boards applied to computer graphics and supporting communication signal processing and information assurance products.
• What Will You Do:
• Identify requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration.
• Recommend new tools and practices for continuous improvement in the group’s ASIC / FPGA design flow.
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status.
• Participate in Agile team meetings and planning activities
• Qualifications You Must Have:
• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
• The ability to obtain and maintain a U.S. government issued security clearance is required
• U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
• At least 3+ years e experience in RTL coding and simulation in Verilog or VHDL.
• Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
• Experience in Testbench development for the verification of RTL blocks using System Verilog.