Senior DFT Engineer - Hardware

POR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect, Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics.

Ability to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.

Solve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.

Work with powerful Industry-standard tools for Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.

Partnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.

Btech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience

Solid Analytical and Problem Solving skills.

Good understanding and Exposure to Logic design, Architecture & Verification

Strong background in DFT Engineering and Post Si DFX Productization

Strong Coding skills in industry standard scripting languages.

5+ yrs of experience in DFT and/or Industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, X prop, etc. will be plus.

Outstanding written and oral communication skills with the curiosity to learn.