Senior Design Verification Engineer, Silicon

Responsibilities

• Develop verification plans and test plans for digital intellectual properties (IPs) and subsystems.
• Create and utilize verification components and testbench environments for digital logic at RTL using SystemVerilog and industry-standard methodologies such as VMM, OVM, or UVM.
• Execute gate-level simulations (GLS) and Unified Power Format (UPF)-based power simulations, performing debugging to deliver high-performance and low-power hardware.
• Drive coverage-driven verification strategies to ensure complete verification closure for ASICs or FPGAs.
• Utilize scripting languages like Perl or Python to create automation and support various verification techniques.
• - Develop verification plans and test plans for digital intellectual properties (IPs) and subsystems. - Create and utilize verification components and testbench environments for digital logic at RTL using SystemVerilog and industry-standard methodologies such as VMM, OVM, or UVM. - Execute gate-level simulations (GLS) and Unified Power Format (UPF)-based power simulations, performing debugging to deliver high-performance and low-power hardware. - Drive coverage-driven verification strategies to ensure complete verification closure for ASICs or FPGAs. - Utilize scripting languages like Perl or Python to create automation and support various verification techniques.

Minimum qualifications:

Preferred qualifications:

Qualifications

• Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs. - Experience verifying digital IP and subsystems. - Experience working with design verification (DV) testbenches or environments. Preferred qualifications: - Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - Experience with verification planning, testplan development, and coverage-driven verification closure. - Experience creating and using verification components in VMM, OVM, or UVM. - Experience with UPF-based power simulations and gate-level simulation (GLS) debugging. - Familiarity with ASIC standard interfaces (e.g., MIPI, ARM AMBA, UART, I2C) and scripting languages like Perl or Python.