Senior Design Verification Engineer, Silicon

Responsibilities

• Plan the verification of complex digital design blocks at sub system level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• - Plan the verification of complex digital design blocks at sub system level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. - Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

Preferred qualifications: