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indeed

Senior Design Verification Engineer

SiFive
IND
Full-time
Onsite
Discovered 1 weeks ago
ASIC, SoC, and IP design verificationOut-of-order CPU coresSystemVerilogUVMCPU micro-architectureConstrained-random verification
Free

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ASIC, SoC, and IP design verificationOut-of-order CPU coresSystemVerilog
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About SiFive

SiFive develops RISC-V compute platforms for applications including artificial intelligence, automotive, data centers, mobile, and consumer systems.

The company emphasizes collaboration, innovation, and processor design.

Role Summary

Own block- and subsystem-level design verification for advanced out-of-order CPU cores.

Work with micro-architects and RTL designers to verify execution pipelines, memory systems, and coherence protocols.

The role is based in India and requires 5–10 years of design verification experience.

Verification Planning and Ownership

  • Drive verification for CPU front-end, rename, issue, execution, retirement, load-store, cache, TLB, and coherence blocks.
  • Derive verification plans from architecture and micro-architecture specifications covering speculation, hazards, memory ordering, and coherence.

Testbench and Environment Development

  • Develop and maintain SystemVerilog and UVM testbenches with agents, monitors, scoreboards, and reference models.
  • Create constrained-random and directed tests for out-of-order corner cases.
  • Implement self-checking mechanisms for retirement, memory ordering, atomics, fences, TLBs, and privilege flows.

Coverage and Quality

  • Define and track functional, code, and assertion coverage and add tests or monitors to close gaps.
  • Create SVA assertions for deadlock, livelock, mispredict, exception, interrupt, flush, forwarding, and hazard properties.
  • Analyze regressions, triage failures, and drive issues to closure.

Debug and Collaboration

  • Debug speculation, replay, memory ordering, TLB, MMU, privilege, and protection failures.
  • Collaborate with micro-architecture, RTL, performance, modeling, and post-silicon validation teams.

Methodology and Mentoring

  • Contribute to DV methodology improvements covering UVM components, coverage strategies, and regression flows.
  • Guide junior engineers through testbench design, stimulus generation, debugging, and code reviews.

Required Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 5–10 years of ASIC, SoC, or IP design verification experience.
  • Direct experience verifying out-of-order or superscalar CPU cores or similar high-performance pipelines.
  • Strong SystemVerilog and UVM skills, CPU micro-architecture knowledge, and coverage-driven verification experience.
  • Experience with SVA, industry-standard simulators, and verification debug tools.

Employment Conditions

  • Employment is contingent on successful background and reference checks.
  • The position requires authorization to work in India and access to export-controlled technology under applicable requirements.

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