Senior Design Verification (DV) Engineer

We’re looking for highly experienced Design Verification Engineers (DVE) in the United States.

The DVE is responsible for developing and verifying silicon IP.

The DVE should have hands-on experience taking leading-edge digital silicon IP from idea to bring-up, working with Architecture/Micro-architecture, PD, and Software teams.

• Develop, optimize, and verify digital silicon IP using an existing C or Python model
• Create and maintain specifications, block diagrams, and detailed documentation/user guides
• Characterize the performance of digital silicon IP using industry standard tools and flows, including FPGA simulation and emulation

• At least 10 years of experience in Design Verification
• Experience leading a team of Design Verification Engineers
• Bachelors/Master's degree in Electrical Engineering
• Experience with Synopsys tools and advanced node processes (below 12nm) is preferred
• Startup experience is preferred
• Government clearance is preferred

Compensation Range: $150,000–$220,000 per year (California).

This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.