RTL Design / Microarchitecture Engineer

• Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)
• Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces)
• Experience working in ASIC/SoC development environments

• Experience in one or more domains:
• CPU, GPU, AI/ML accelerators, networking, or high-speed data processing
• CPU, GPU, AI/ML accelerators, networking, or high-speed data processing
• Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency)
• Familiarity with low-power design techniques (clock gating, power domains)
• Exposure to formal verification or linting tools
• Experience with GLS, SDF annotation, and silicon debug
• Scripting skills (Python/TCL) for automation
• Understanding of hardware-software interaction (firmware, drivers)

Range: $160,000–$220,000 per year (California).

This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.

• Medical, Dental, & Vision - 100% covered premiums

• 401(k) match
• WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect.

As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.