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Senior CPU Design Verification Engineer
SiFive
IND
Full-time
Onsite
Discovered 1 weeks ago
ASIC/SoC/IP design verificationOut-of-order CPU coresCPU micro-architectureSystemVerilogUVMConstrained-random verification
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ASIC/SoC/IP design verificationOut-of-order CPU coresCPU micro-architecture
Role Overview
Own block- and subsystem-level design verification for advanced out-of-order CPU cores.
Work with micro-architects and RTL designers to verify execution pipelines, memory systems, and coherence protocols using coverage-driven methods.
Key Skills for This Role
ASIC/SoC/IP design verificationOut-of-order CPU coresCPU micro-architectureSystemVerilogUVMConstrained-random verification
Full Job Posting
About SiFive
SiFive develops RISC-V compute platforms for applications including artificial intelligence, automotive, data centers, mobile, and consumer products.
Role Summary
Own block- and subsystem-level design verification for advanced out-of-order CPU cores.
Work with micro-architects and RTL designers to verify execution pipelines, memory systems, and coherence protocols using coverage-driven methods.
Verification Planning and Ownership
- Drive verification for CPU front-end, rename, issue and execution, reorder buffer, retirement, exception, flush, load-store, cache, TLB, MMU, and coherence blocks.
- Derive verification plans from architecture and micro-architecture specifications, including speculative execution, pipeline hazards, memory ordering, and cache interaction.
Testbench and Environment Development
- Develop and maintain SystemVerilog/UVM testbenches with agents, monitors, scoreboards, reference models, constrained-random stimulus, and directed tests.
- Implement self-checking for instruction retirement, architectural state, load-store ordering, atomics, fences, TLBs, page tables, and privilege flows.
Coverage, Quality, and Debug
- Define and track functional, code, and assertion coverage and add tests or monitors to close gaps.
- Create SVA assertions for deadlock, livelock, mispredicts, exceptions, interrupts, flush paths, forwarding, and hazard resolution.
- Analyze regression results, triage failures, and debug speculation, replay, memory consistency, TLB, MMU, and privilege issues.
Collaboration and Mentoring
- Collaborate with micro-architecture, RTL, performance, modeling, post-silicon, and validation teams.
- Improve verification methodology, conduct code reviews, and guide junior engineers on testbench design, stimulus generation, and debug.
Required Qualifications
- BS or MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Typically 5–10 years of ASIC, SoC, or IP design verification experience.
- Direct experience verifying out-of-order or superscalar CPU cores or closely related high-performance pipelines.
- Strong proficiency in SystemVerilog and UVM or an equivalent class-based verification methodology.
- Hands-on experience with constrained-random verification, coverage-driven verification, and SVA assertions.
- Experience with simulators such as VCS, Xcelium, or Questa and debug tools such as Verdi or DVE.
- Strong problem-solving, debugging, communication, teamwork, and independent execution skills.
Work Authorization
- The position requires satisfactory proof of the right to work in India.
- Employment is contingent on background and reference checks and authorization to access export-controlled technology or obtain required approvals.
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