Senior Circuit Silicon Correlation DFT Engineer

Participate in ground breaking Processor design and debug in deep submicron technologies.

Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.

Responsible for generating ATPG patterns for Silicon speed path debug.

RTL and gate level verification for ATPG, non-ATPG patterns.

Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.

RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon

Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run

Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.

BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.

Good understanding of Design-for-test(DFT) and logic design is required.

Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.

Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.

Basics of circuits and RAM functionality/architecture will be helpful.

Experience in VLSI simulation tools like VCS etc

Experience with pattern generation using tools such as tessent.

Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.