Senior ASIC Design Engineer

As a key member of our design team, you will be responsible for the micro-architecture and build implementation of NOC/interconnect Xbar.

Micro-architect features to meet area, performance, and power requirements.

Deliver a fully verified build by working closely with verification engineers.

Deliver a synthesis/timing clean build to ensure a routable and physically implementable design.

Collaborate with architects, verification engineers, software engineers, and physical build engineers to accomplish your goals.

Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.

8+ years of build/RTL experience working on complex units in xbar/memory system.

Highly proficient in logic design, Verilog and/or System-Verilog, with a solid understanding of Computer Architecture and Digital Systems build.

A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug.

Strong interpersonal and communication skills to collaborate across teams.

Prior experience building arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.

Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, and virtual channels.

Good debugging and analytical skills.

You will also be eligible for equity and benefits .

This posting is for an existing vacancy.

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