Senior ASIC Design Engineer - NOC IP

Own micro-architecture and RTL development of design modules.

Micro-architect features to meet performance, power and area requirements.

Work with HW architects to define critical features.

Collaborate with verification teams to verify the correctness of implemented features.

Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.

Work on post-silicon verification and debug.

BS / MS or equivalent experience.

7+ years of design experience.

Experience in RTL design of complex design units for at least two or three projects.

Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Expertise in Verilog.

Design experience in memory subsystem or network interconnect IP.

Good debugging and problem solving skills.

Scripting knowledge (Python/Perl/shell).

Leadership experience in leading small 2-3 member teams.

Good interpersonal skills and ability & desire to work as a part of a team.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

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