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RTL Design Engineer
Apple
Los Angeles, USA
Full-time
Senior · 10+ years experience
Onsite
Discovered 1 weeks ago
VerilogSystemVerilogVerilog simulatorslintersclock-domain crossing checkersSynthesis
Free
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VerilogSystemVerilogVerilog simulators
Key Skills for This Role
VerilogSystemVerilogVerilog simulatorslintersclock-domain crossing checkersSynthesis
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Description
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.
Minimum Qualifications
- BS and a minimum of 10 years relevant industry experience
Preferred Qualifications
- Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
- Synthesis, static timing analysis, and design-for-test (DFT)
- SystemVerilog assertions, checkers, and advanced verification techniques
- Scripting languages (Perl, Python)
- Formal verification and low-power design methodologies
- Hardware-software co-design and system-level optimization
- Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
- Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design
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