lever
RTL Design Engineer
Mythic
Austin, USA
Full-time
Mid · 3+ years experience
Hybrid
USD 120000-225000 yearly / year
Discovered 1 weeks ago
VerilogSystemVerilogSynthesisStatic Timing Analysis
Free
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VerilogSystemVerilogSynthesis
Key Skills for This Role
VerilogSystemVerilogSynthesisStatic Timing Analysis
Full Job Posting
- Design and implement RTL for Mythic's next-generation AI processor.
- Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
- Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
- Drive timing closure by working with synthesis and physical design teams.
- Participate in design reviews and contribute to improving RTL coding practices and methodologies.
- Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
- 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
- Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
- Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
- Familiarity with timing constraints, physical design considerations, and EDA flows.
- Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
- Strong problem-solving and communication skills with ability to work in cross-functional teams.
About Mythic
Semiconductors97 employees
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