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Principal Verification Engineer
Altera
Remote, IND
Full-time
Senior · 10+ years experience
Remote
Discovered 3 weeks ago
SystemVerilogUVMVerilogVHDLPythonPerl
Free
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Role Overview
Altera is looking for a talented and driven Principal Verification Engineer to Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
Key Skills for This Role
SystemVerilogUVMVerilogVHDLPythonPerl
Full Job Posting
Job Description:
Altera is looking for a talented and driven Principal Verification Engineer to Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
Key Responsibilities
- Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
- Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
- Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
- Develop verification components, including drivers, monitors, scoreboards, and checkers.
- Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
- Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
- Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
- Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
- Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.
Qualifications:
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