indeed
Principal/Team Lead, Digital Verification Engineer (FEC)
Ciena
Ottawa, CAN
Full-time
Onsite
$133,100 to $212,500.
Discovered 1 weeks ago
Digital verificationForward Error Correction (FEC)C/C++SystemVerilogUVMSystemVerilog Assertions (SVA)
Free
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Digital verificationForward Error Correction (FEC)C/C++
Role Overview
Develop verification strategies for Ciena's Forward Error Correction IP within its Wavelogic modem product family.
Collaborate with digital design engineers, verification engineers, DSP modelers, systems engineers, and architects.
Report to the ASIC Senior Manager.
Key Skills for This Role
Digital verificationForward Error Correction (FEC)C/C++SystemVerilogUVMSystemVerilog Assertions (SVA)
Full Job Posting
Role overview
Develop verification strategies for Ciena's Forward Error Correction IP within its Wavelogic modem product family.
Collaborate with digital design engineers, verification engineers, DSP modelers, systems engineers, and architects.
Report to the ASIC Senior Manager.
Responsibilities
- Read FEC architecture and functional requirements specifications and collaborate with technical stakeholders.
- Develop verification, functional coverage, and formal verification test plans.
- Validate FEC functional blocks using simulation, formal, and coverage methods.
- Create SystemVerilog UVM and C++ testbench environments, agents, scoreboards, and test scenarios.
- Perform coverage-driven verification, monitor regressions, and debug failures.
- Report verification progress, communicate risks, and mentor or supervise junior engineers.
Must-have qualifications
- 10+ years of verification experience.
- Minimum bachelor's degree in Electrical, Computer, or Software Engineering.
- Significant experience with C/C++, SystemVerilog, UVM, SVA, and major-vendor simulators.
- Ability to define comprehensive digital verification and coverage strategies.
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