Principal SoC RTL Design Engineer

Bachelor’s/Master’s degree in Electrical Engineering or related field

8+ years of relevant experience in RTL design and micro-architecture

Strong expertise in:

Verilog/SystemVerilog

Digital design fundamentals

High-performance and low-power design techniques

Experience designing for large SoCs in AI, HPC, or Networking domains

Solid understanding of high-speed IO protocols : UCIe, PCIe, Ethernet

Experience with multi-clock, high-bandwidth, and latency-sensitive designs

Strong debugging and problem-solving skills

Experience with memory interfaces (DDR, HBM, LPDDR)

Familiarity with coherency protocols and interconnect fabrics

Exposure to synthesis, STA, and physical design constraints

Experience with emulation or FPGA prototyping

Working knowledge of scripting (Python, Tcl)

Strong ownership and attention to detail

Focus on quality and first-pass silicon success

Ability to work across teams in a fast-paced environment

Bias toward scalable, reusable, and clean design

High-quality RTL with minimal re-spins

Successful integration into complex SoCs

Performance, power, and area targets met

Contribution to reusable IP and design frameworks

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.