Principal Packaging Engineer

Responsibilities

• Design high-speed IC packages and Chip-On-Board (COB) solutions to meet new product technical and financial requirements; develop robust solutions that achieve the highest levels of quality and reliability in fast-paced Datacenter connectivity environments.
• Perform 3D signal integrity modeling at silicon, package, and system levels, including experimental validation via Scattering Parameter (S-parameter) and Time-Domain Reflectometer (TDR) measurements where required.
• Prepare technical reports and application notes for internal teams and external customers/suppliers, covering Signal and Power Integrity (SI/PI), PCB layout guidance, and assembly process instructions.
• Design and produce PCB and high-density substrate layouts for reliability qualification and electrical performance evaluation.
• Serve as technical interface with manufacturing suppliers throughout new product introduction (NPI), package definition, and design phases; drive alignment between design intent and manufacturing capability.
• Identify, evaluate, and launch projects with new strategic suppliers and emerging package technologies to advance Semtech's packaging roadmap.
• Mentor junior packaging engineers and contribute to continuous improvement of design methodologies, tools, and workflows.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Physics Engineering, or a related field, with 8+ years of experience as an IC Package Design Engineer or Signal Integrity Engineer.
• Deep expertise in high-speed transmission line theory, multi-domain power delivery network (PDN) design, and package-level signal integrity — including crosstalk, impedance control, and return-loss optimization.
• Hands-on proficiency with industry-standard EDA tools: Keysight Advanced Design System (ADS), Cadence Advanced Package Designer (APD/SiP), and Ansys HFSS.
• Demonstrated experience with RF/SI measurement equipment including Vector Network Analyzers (VNA) and Time-Domain Reflectometers (TDR).
• Familiarity with multiple advanced packaging technologies: 2D, 2.5D, 3D, Fan-In, Fan-Out (FOCOS), high-density substrate, silicon bridge interconnects, and Chip-On-Board (COB).
• Experience in optoelectronics package design or opto-electronic assembly is a strong asset.
• Working knowledge of JEDEC specification JESD47H (Stress-Test-Driven Qualification of Integrated Circuits) and its design implications.
• Proven ability to manage supplier relationships and drive technical alignment throughout NPI and package qualification phases.
• Strong written and verbal communication skills, with the ability to produce high-quality technical documentation for both internal and customer-facing audiences.

Desired Qualifications

• Master's degree or Ph.D. in Electrical Engineering, Physics, or a related discipline.
• Experience with opto-electronic package assembly and photonic integration is highly desirable.
• Background in Datacenter or high-speed communications product development (400G, 800G, 1.6T).
• Familiarity with thermo-mechanical simulation tools and reliability engineering methodologies (e.g., finite element analysis for package stress modeling).
• Experience working in a fabless semiconductor environment with global contract manufacturing partners.

Career Growth Philosophy