Principal Engineer – Physical Design

Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

Own end-to-end physical design implementation for large hierarchical blocks, from floorplanning to GDSII signoff.

Develop and optimize flows for placement, clock tree synthesis (CTS), routing, and timing closure.

Analyze and optimize IR drop, EM, congestion, and power to meet stringent chip targets.

Collaborate with RTL, DFT, STA, and power teams to resolve cross-domain issues and ensure robust closure.

Define and maintain best practices, scripts, and automation flows (Tcl, Python, or Make-based).

Lead timing, physical verification (DRC/LVS), and ECO closure at the block and top level.

Provide technical leadership for floorplan architecture, partitioning, and clock distribution strategies.

Drive design convergence on multi-corner multi-mode (MCMM) analysis and ensure signoff consistency.

Partner with CAD and Foundry teams for technology evaluation, library bring-up, and methodology improvement.

Mentor and guide junior engineers, fostering a strong technical culture within the PD organization.

10–15+ years of experience in deep-submicron physical design for complex SoCs or ASICs.

Proven expertise in Cadence Innovus PNR tool.