Principal Engineer – Design Verification

Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

IP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.

UVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.

Test Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).

Advanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.

Lead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.

Cross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.

Experience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.

Domain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.

Methodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.