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Principal Engineer, Design for Test (DFT)
Ayar Labs
Bengaluru, IND
Full-time
Senior · 12+ years experience
Onsite
Discovered 3 weeks ago
ATPGMBISTJTAGboundary scanRTL-to-GDSIIPython
Free
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ATPGMBISTJTAG
Key Skills for This Role
ATPGMBISTJTAGboundary scanRTL-to-GDSIIPython
Full Job Posting
- Define and drive SoC-level DFT architecture and implementation strategy for advanced ASIC and electro-optical SoCs
- Lead scan insertion, ATPG generation, MBIST/LBIST integration, JTAG/boundary scan, and compression methodologies
- Develop and validate DFT constraints, timing requirements, and test modes in collaboration with RTL and Physical Design teams
- Drive fault coverage closure, pattern validation, and silicon test debug activities
- Collaborate with ASIC, AMS, Packaging, Firmware, Validation, and Product Engineering teams to ensure successful silicon bring-up and production readiness
- Support post-silicon validation, characterization, yield analysis, and manufacturing ramp activities
- Develop automated methodologies, flows, and infrastructure to improve DFT quality and execution efficiency
- Drive root-cause analysis for silicon test failures and manufacturing issues
- Work closely with EDA vendors and external partners on DFT tool flows and methodologies
- Mentor engineers and provide technical leadership across DFT and related domains
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in ASIC/SoC DFT implementation and silicon bring-up
- Strong expertise in: Scan architecture and scan compression, ATPG and fault coverage analysis, MBIST/LBIST methodologies, JTAG and boundary scan, At-speed testing and silicon debug and DFT signoff and manufacturing test flows
- Strong knowledge of RTL-to-GDSII ASIC development flows
- Experience with industry-standard DFT and ATPG tools
- Strong understanding of timing constraints, clocking architectures, and multi-clock domain designs
- Experience debugging silicon and supporting high-volume manufacturing
- Strong scripting and automation skills using Python, Tcl, or similar languages
- Excellent debugging, problem-solving, and cross-functional collaboration skills
- Experience with advanced-node SoCs and chiplet-based architectures
- Experience with high-speed SerDes, UCIe, PCIe, CXL, Ethernet, or optical interconnect technologies
- Experience with mixed-signal integration and electro-optical systems
- Experience with silicon bring-up, yield improvement, and production ramp
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