Principal Engineer

• Lead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs.
• Develop robust constraint-random verification environments from scratch using SystemVerilog and UVM methodologies.
• Build reusable verification components, assertions, coverage models, and testbenches to ensure comprehensive design validation.
• Verify ARM-based IPs and SoCs with strong understanding of AHB, AXI, and serial communication protocols.
• Perform RTL verification, power-aware simulations, Gate-Level Simulations (GLS), boot verification, and drive end-to-end verification closure.
• Develop C-based tests, debug complex functional issues using Tarmac, and collaborate closely with design and software teams.
• Drive automation initiatives to improve verification productivity, coverage, and quality.
• Mentor and guide junior engineers while promoting verification best practices across the team.

Your profile Qualifications and skills to help you succeed

• Strong expertise in Verilog/SystemVerilog, UVM, C programming, and Tarmac debugging .
• Proven experience in IP and SoC verification , including verification planning, component development, assertion coding, and constrained-random verification.
• Experience leading or contributing to the development of verification architectures and UVM environments from scratch at subsystem and SoC levels.
• Hands-on experience in RTL verification, Power-Aware Verification, Gate-Level Simulation (GLS), and Boot Verification .
• Strong knowledge of ARM-based architectures , AHB/AXI protocols , and industry-standard serial interfaces.
• Experience with verification automation, coverage closure, regression management, and verification signoff activities.
• Strong analytical, debugging, leadership, and stakeholder management skills.
• Ability to mentor engineers and drive verification excellence on complex SoC programs.

#WeAreIn for driving decarbonization and digitalization.

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