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Principal DFT Engineer
Analog Devices, Inc.
Bengaluru, IND
Full-time
Senior · 10+ years experience
Onsite
Discovered 3 weeks ago
Synopsys DFT CompilerTessentCadence ModusATPGTCLPython
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Synopsys DFT CompilerTessentCadence Modus
Role Overview
The Principal Digital DFT Engineer is responsible for architecting, implementing, and verifying advanced DFT solutions for complex digital ASICs and SoCs. This position emphasizes direct technical execution, deep problem-solving, and ownership of DFT flows for robust testability and manufacturing yield.
Key Skills for This Role
Synopsys DFT CompilerTessentCadence ModusATPGTCLPython
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About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .
Role Summary
The Principal Digital DFT Engineer is responsible for architecting, implementing, and verifying advanced DFT solutions for complex digital ASICs and SoCs. This position emphasizes direct technical execution, deep problem-solving, and ownership of DFT flows for robust testability and manufacturing yield.
Key Responsibilities
- Own and drive all aspects of DFT architecture, definition, and implementation for digital chips, including scan insertion, ATPG, boundary scan, MBIST, logic BIST, JTAG and test compression techniques.
- Hands-on execution with EDA tools for scan synthesis, test pattern generation, fault simulation, and DFT rule checks.
- Create and validate test plans targeting high coverage for stuck-at, transition, and critical path faults.
- Integrate DFT with RTL and physical design teams; resolve complex trade-offs impacting fault coverage, PPA, or manufacturability.
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