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Pre-si Verification Engineer
Intel
Bengaluru, IND
Full-time
Senior · 8+ years experience
Hybrid
Discovered 3 weeks ago
System VerilogUVM
Free
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System VerilogUVM
Role Overview
The Client Engineering Group is looking for a highly motivated Pre-Si SoC Verification Engineer to join the graphics instead die frontend design and verification team for the next generation of Client SOC.
In this role, the candidate's responsibilities include, although not limited to: Responsible for ensuring functional correctness and quality of SoC designs before silicon tape-out, through simulation, emulation, and advanced verification methodologies.
The role involves testbench development, coverage-driven verification, and debug of complex SoC architectures.
Key Skills for This Role
System VerilogUVM
Full Job Posting
Job Description:
The Client Engineering Group is looking for a highly motivated Pre-Si SoC Verification Engineer to join the graphics instead die frontend design and verification team for the next generation of Client SOC. In this role, the candidate's responsibilities include, although not limited to: Responsible for ensuring functional correctness and quality of SoC designs before silicon tape-out, through simulation, emulation, and advanced verification methodologies. The role involves testbench development, coverage-driven verification, and debug of complex SoC architectures.
Qualifications:
- Experience : 8 to 15 years
- Key Responsibilities • Define and develop SoC / subsystem / IP verification plans aligned to architecture specifications • Build and maintain System Verilog/UVM-based testbenches and verification environments • Develop constrained-random and directed test scenarios and validation content • Execute simulation and emulation-based verification to validate functionality, power, and performance • Perform debug and root-cause analysis of RTL and testbench failures in pre silicon environment • Analyze and drive functional, code, and assertion coverage closure • Collaborate with architecture, RTL design, post silicon, and validation teams • Document verification plans and participate in design/verification reviews • Continuously improve verification methodology, infrastructure, and automation flows • Incorporate learning from post silicon validation to enhance future verification coverage • Good at leveraging AI across verification coding, debugging , quality sign-off requirements. • Minimum 8-15 year of relevant experience in SoC/subsystem/IP level verification • Qualifications BE or B Tech or M Tech ECE or Computer Science with 8-15 years front-end pre-si verification.
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