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Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru.
In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.
The ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug.
This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.
Key Responsibilities-
• Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.
• Develop and drive architecture and circuit implementation for:
• High-speed TX and RX circuits
• Serializer/Deserializer (SerDes) building blocks
• PLLs, DLLs, CDRs, and clocking circuits
• Equalization and signal conditioning circuits
• Bandgap references, bias generation, and LDOs
• ESD protection and IO pad circuitry
• Perform detailed transistor-level design, simulation, and verification across multiple PVT corners.
• Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.
• Collaborate closely with physical design teams on layout reviews and post-lay out optimization.
• Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.
• Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.
• Mentor junior engineers and contribute to team-wide design methodologies and best practices.
• Drive technical reviews and provide leadership in solving complex design challenges.
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Intel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products. The ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation. Key Responsibilities- • Lead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces. • Develop and drive architecture and circuit implementation for: • High-speed TX and RX circuits • Serializer/Deserializer (SerDes) building blocks • PLLs, DLLs, CDRs, and clocking circuits • Equalization and signal conditioning circuits • Bandgap references, bias generation, and LDOs • ESD protection and IO pad circuitry • Perform detailed transistor-level design, simulation, and verification across multiple PVT corners. • Drive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability. • Collaborate closely with physical design teams on layout reviews and post-lay out optimization. • Support silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements. • Work with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution. • Mentor junior engineers and contribute to team-wide design methodologies and best practices. • Drive technical reviews and provide leadership in solving complex design challenges.
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Design and manufacture of semiconductors and computing technology.
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Senior · 5+ years experience
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